Modern computer systems are becoming more diverse and energy‑efficient. Heavy compute is offloaded to accelerators (GPU, FPGA, AI chips). Fast intelligent networks run functions in the fabric, bringing processing nearer data and easing load on compute nodes. Object stores replace limited POSIX file systems. The main drivers are AI’s massive compute demand and the need for energy efficiency. The three pillars, (1) heterogeneous processors, (2) smart high‑performance networks, and (3) new storage, force continual redesign of algorithms and software. Future architectures may require new mathematical algorithms and implementation strategies. To keep development costs manageable across varied hardware, performance portability and productivity are essential. Early decisions on algorithm design and variants help stay aligned with evolving hardware, meet performance goals, and ensure sustainability. Developers and AI/HPC operators gain optimization chances, e.g., performance impact of network topology and usage of smart NICs may boost application and system throughput.
The HPCLab develops algorithmic and software solutions for the efficient implementation of data-driven optimization and decision workflows on near-future processor architectures and memory technologies. Our focus is on optimization methods and simulation workflows designed and developed in the MODAL Labs EnergyLab, MedLab, MobilityLab, NanoLab, and SynLab.
Projects
In the third phase of the Research Campus MODAL, the HPCLab develops and refines solutions beneficial for application developers and system operators for leveraging heterogeneous systems, interconnects and object stores. In close cooperation with industrial and academic partners, including Intel, Cornelis Networks, and international research partners, the lab addresses key challenges in heterogeneous computing, high-speed interconnects and and fast object stores.
Performance and energy efficiency of heterogeneous systems.
We assess performance and portability on emerging processors using NextSilicon’s data‑flow design. We benchmark compute power and energy efficiency for MODAL algorithms, tune compilers on NextSilicon, and optimise Nvidia, Intel, AMD GPUs (and optional FPGAs). In phase three, with NHR support, we focus on energy‑efficiency by gathering data, monitoring workflows, and running synthetic benchmarks of typical workloads. Energy analysis uses tools such as Energy‑Aware Runtime, perf, VTune, and LIKWID. HPCLab will share optimisation knowledge and deliver best‑practice guidelines to all MODAL teams.
Intelligent high-performance interconnects.
In partnership with Cornelis Networks we are building a next‑generation Omni‑Path testbed to examine how network topology impacts AI/ML node performance and overall throughput, while also evaluating the benefits of programmable Host Fabric Interfaces (Smart NICs) on that platform; this research explores the synergy between configurable network hardware, development tools, and the resulting functional and performance improvements.
HPC object store DAOS.
Partnering with Cornelis Networks and Intel, we are boosting the next‑generation Omni‑Path interconnect to better support Intel DAOS and evaluating its native key‑value store for MODAL‑relevant application patterns.
Past Projects
